hardware instruction
英 [ˈhɑːdweə(r) ɪnˈstrʌkʃn]
美 [ˈhɑːrdwer ɪnˈstrʌkʃn]
网络 硬体的指令; 硬件指令
双语例句
- The hardware architecture and instruction set of the digital signal processor leads to its high speed and precision in processing data.
数字信号处理器的硬件结构和指令体系决定了它在实现各种算法时具有速度快、精度高的特点。 - With consideration of the working principle and functions of the AVC system, the possibility of causing an abnormal generator outage by the AVC system is analyzed and eliminated. The possibility includes misadjustment, hardware faults, and adjustment instruction mistakes.
通过一起发电机非正常停机事件，联系AVC系统的原理及功能，分析并排除了在这次非正常停机事件中，AVC系统可能引起停机的各种可能性（包括误调节、硬件故障及调节指令错误等）。 - The paper introduces the installation? file configuration and hardware simulation logic structure of instruction level simulator.
介绍指令级模拟器SkyEye及安装、文件配置、硬件模拟逻辑结构。 - High performance approach with both hardware feasibility and software effectiveness for solving instruction interlock problem is given.
最后，给出了一种兼顾硬件可行性与软件有效性的解决指令互锁的高性能方案。 - This paper has introduced a method of the software and hardware of the multi-medium computer aid instruction system.
介绍了一种计算机辅助多媒体考试系统的软、硬件设计方案。 - The cloud environment is constructed with software and hardware components chosen by the team; however, the article contains knowledge and instruction that can be used regardless of technologies you choose.
该团队使用选定的软件与硬件组件构建这个云环境；然而，无论您选择何种技术，都能用到本文包含的知识与说明。 - Based on the study and analysis of the DAISY and the Crusoe ( tm), a hardware oriented model for dynamic instruction translation is proposed.
文章在研究分析DAISY和Cruseo（tm）这两款处理器后，针对X86指令集系统提出一种全硬件的动态翻译模型。 - The method made use of hardware dynamic instruction schedule technique which applied both instruction level parallelism and thread level parallelism to improve the parallel computation performance. 3.
该方法利用硬件动态指令调度技术，同时采用指令级并行和线程级并行，提高并行运算的性能。 - Based on the design of demultiplexing and parsing procedure of MPEG-2 tranSPort stream, this paper presents the hardware/ software co-design of the embedded RISC core, especially for the limited instruction cache size.
本文以符合ATSC标准的MPEG－2TS流解复用和系统信息解码为算法对象，研究在片上指令缓存有限的情况下设计嵌入式RISC核时，系统层解码的软／硬件协同设计。 - The digital signal processor becomes the preferred utility for realizing digital arithmetic rapidly and precisely relying on its particular hardware and instruction architecture.
而DSP（数字信号处理器）以其特有的硬件体系结构和指令体系成为快速精确实现数字信号处理算法的首选工具。